1. Field of the Invention
The present invention generally relates to electrical fuses in microelectronic devices and a method of making metal fuses. In particular, the invention relates to damaging a metal structure to control the location of fuse blow.
2. Description of Related Art
In advanced technologies, e-fuses have been implemented at the gate level where a fuse structure includes a narrow, horizontal, polycrystalline silicon (herein “poly”) line topped by a silicide. During programming, a high current (i.e. high current density) is passed through the structure. High current density causes the silicide to irreversibly migrate from the top of the poly to throughout the line, causing a change in resistance and thus acting as a programmable fuse. In poly fuses, the fuse structure is often placed over oxide isolation areas. The dielectric properties of the isolation oxide keep in the heat generated by current flow, thus increasing the temperature of the structure. The increased temperature further enhances migration, thus aiding fuse blow. In addition, air cavities are sometimes formed around the poly line to further increase the heat retention because air is a better dielectric than isolation oxides.
As scaling progresses, it is becoming harder to implement fuses at the poly level due to drop in maximum allowable currents through the first metal layer or conductor. Also, the collateral damage (namely movement of fuse material causing neighboring dielectric material to fracture) associated with fuse blow is becoming more difficult to contain. Furthermore, the horizontal structure of the fuse consumes valuable chip real estate. As a result, there is a drive to implement fuses vertically at the metal interconnect levels and use the phenomenon of electromigration (EM) to program the fuses.
In a conventional metal fuse approach, as shown in FIG. 1, a two-level structure comprises conductor 11 embedded in dielectric layer 10, and via 21 and line 22 embedded in dielectric layer 20. A cap layer 23 is typically deposited over line 22 and dielectric layer 20. Electron flow is from via 21 into line 22. A high current is applied between the positive current connection (I+) and negative current connection (I−) to induce EM failure. Voltage across the structure is measured using the positive (V+) and negative (V−) voltage connections. The electron flow through the fuse structure is from the lower level metal, conductor 11, to the upper level metal, line 22. The intent is to have a failure (i.e. fuse blow) in via 21. However, with this design, some of the failures (i.e. fuse blows) occur in via 21 while other failures occur in line 22. The lack of control over the failure location results in variability in the final resistance of the fuse structure after programming.
Therefore, a structure is needed such that fuse blow occurs repeatedly and reliably at the same location. At the same time, the structure must reliably conduct current prior to fuse blow.